Self-correcting multiphase clock recovery

ABSTRACT

A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, creating error signals for each of the multiphase clock signals using the data stream, selecting at least one of the error signals based on retime state signals, correcting the multiphase clock signals using the error signal to produce corrected multiphase clock signals, and sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal. The multiphase clock signals may be subharmonics of the data stream. In one embodiment, an UP error signal and a DN error signal are created for each of the multiphase clock signals, wherein the selecting step selects one of the UP error signals and one of the DN error signals, and the selected UP error signal and the selected DN error signal are applied to inputs of a charge pump to correct the clock signals. A multiphase voltage-controlled oscillator may be used to provide the multiphase clock signals. The retime state signals are defined using the synchronization states.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related to U.S. patent application Ser. No.__/______ entitled “MULTIPHASE CLOCK RECOVERY USING D-TYPE PHASEDETECTOR” (attorney docket number AUS9-2000-0518), filed concurrentlywith this application, which is hereby incorporated.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to electronic clockcircuits, specifically to a method and system for providing clockrecovery from a high-frequency data signal, and more particularly tosuch a method and system that has reduced power dissipation, andacceptable cycle variation (jitter).

[0004] 2. Description of Related Art

[0005] Electronic circuits that provide clock signals are used in a wideassortment of devices, and particularly in computer systems.Microprocessors and other computer components, such as random accessmemory (RAM), device controllers and adapters, use clock signals tosynchronize various high-speed operations. These computer clock circuitsoften use a phase-lock loop (PLL) circuit to synchronize (de-skew) aninternal logic control clock with respect to an external system clock.

[0006] A typical prior art PLL circuit 1 is shown in FIG. 1 and includesa phase/frequency detector (PFD) 2, a chargepump 3, a low-pass filter 4,and a voltage-controlled oscillator (VCO) 5. Phase/frequency detector 2compares two input signals, a reference signal f_(ref) (from theexternal system clock) and a feedback signal f_(fb), and generates phaseerror signals that are a measure of the phase difference between f_(ref)and f_(fb). The phase error signals (“UP” and “DOWN”) from detector 2are used to generate control signals by charge-pump 3 which are filteredby low-pass filter 4 and fed into the control input ofvoltage-controlled oscillator 5. Voltage-controlled oscillator 5generates a periodic signal with a frequency which is controlled by thefiltered phase error signal.

[0007] The output of voltage-controlled oscillator 5 is coupled to theinput f_(fb) of phase/frequency detector 2 directly or indirectlythrough other circuit elements such as dividers 6, buffers (not shown)or clock distribution networks (not shown), thereby forming a feedbackloop. If the frequency of the feedback signal is not equal to thefrequency of the reference signal, the filtered phase error signalcauses the frequency of voltage-controlled oscillator 5 to shift(upwards or downwards) toward the frequency of the reference signal,until voltage-controlled oscillator 5 finally locks onto the frequencyof the reference; following frequency acquisition, phase acquisition isachieved in a similar manner. The output of voltage-controlledoscillator 5 is then used as the synchronized signal (for internal logiccontrol).

[0008] In cases where the incoming data is a self-clocking bit stream,the comparator system may be used to extract (recover) the clockinformation from the data stream itself. Clock extraction for high-speedserial links is usually accomplished using a VCO with a center frequencyN for extracting a clock from a serial data stream modulated at Nbits/sec. The VCO may provide multiple phases for oversampling, asdiscussed in the article by Yang, et al., “A 0.5 um CMOS 4.0 Gbit/sSerial Link Transceiver with Data Recovery Using Oversampling,” IEEEJSSC Vol 33, No. 5 (May 1998), or more commonly offer just a singlephase for direct detection. An example of a single phase D-type phasedetector technique used for non-return-to-zero (NRZ) data is disclosedin the article by Boerstler, “Dynamic Behavior of a Phase-Locked LoopUsing D-Type Phase Detector and Nonlinear Voltage-ControlledOscillator”, IBM Technical Report TR 21.1428 (Mar. 21, 1991).

[0009] For high-bandwidth applications such as in packet switches,maximizing both frequency and density simultaneously is desired, butthis causes power dissipation and/or power density to be a significantproblem. CMOS technology limitations can also limit the speed at whichclock recovery can be accomplished, and operating the clocks at one-halfthe baud rate has been reported, as in Ewen et al., “Single-Chip 1062Mbaud CMOS Transceiver for Serial Data Communication,” ISSCC Digest, Vol38, pp. 32-33 (February 1995).

[0010] In light of the foregoing, it would be desirable to devise animproved method for recovering a high-speed clock from a data signal. Itwould be further advantageous if the method were to result in reducedpower dissipation, while still ensuring acceptable levels of jitter.

SUMMARY OF THE INVENTION

[0011] It is therefore one object of the present invention to provide animproved clock circuit, such as may be used with a microprocessor orother high-performance computer components.

[0012] It is another object of the present invention to provide such aclock circuit which is able to extract a clock signal from a data streamhaving a high data rate.

[0013] It is yet another object of the present invention to provide amethod of recovering clock signal from a data stream which results indecreased power dissipation as compared to the prior art.

[0014] The foregoing objects are achieved in a method of extracting aclock signal from a data stream, generally comprising the steps ofgenerating a plurality of multiphase clock signals, creating a pluralityof error signals, at least one error signal for each of the multiphaseclock signals, using the data stream, selecting at least one of theerror signals based on a plurality of retime state signals, correctingthe multiphase clock signals using the at least one error signal toproduce corrected multiphase clock signals, and sampling the data streamusing one of the corrected multiphase signals to produce a retimed datasignal. The multiphase clock signals may be subharmonics of the datastream. In one embodiment, an UP error signal and a DN error signal arecreated for each of the multiphase clock signals, wherein the selectingstep selects one of the UP error signals and one of the DN errorsignals, and the selected UP error signal and the selected DN errorsignal are applied to inputs of a charge pump to correct the clocksignals. A multiphase voltage-controlled oscillator may be used toprovide the multiphase clock signals. The retime state signals aredefined using the synchronization states.

[0015] The above as well as additional objectives, features, andadvantages of the present invention will become apparent in thefollowing detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The novel features believed characteristic of the invention areset forth in the appended claims. The invention itself, however, as wellas a preferred mode of use, further objectives, and advantages thereof,will best be understood by reference to the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein:

[0017]FIG. 1 is a block diagram illustrating a conventional phase-lockloop;

[0018]FIG. 2 is timing diagram illustrating synchronization and retimingin one implementation of the present invention using a multiphasevoltage-controlled oscillator (VCO) and a D-Type phase-frequencydetector;

[0019]FIG. 3 is a table illustrating synchronization and retiming stateidentification information used according to the present invention;

[0020]FIG. 4 is a table illustrating how the timing correction(early/late) is determined in accordance one implementation of with thepresent invention which uses a D-type phase detector;

[0021]FIG. 5 is a timing diagram illustrating the multiphase clocksignals and synchronization states with clock and data aligned, for theD-type phase detector implementation;

[0022]FIG. 6 is a timing diagram illustrating multiphase clock signalsand synchronization states where the clock lags the data signal, for theD-type phase detector implementation;

[0023]FIG. 7 is a timing diagram illustrating the multiphase clocksignals and synchronization states when the clock leads the data signal,for the D-type phase detector implementation;

[0024]FIG. 8 is a block diagram illustrating a multiphase phase-lockloop using a D-type phase detector in accordance with one embodiment ofthe present invention;

[0025]FIG. 9 is a block diagram of the multiphase phase detector used inthe phase-lock loop of FIG. 8;

[0026]FIG. 10 is a block diagram of the sampled clock unit used in themultiphase phase detector of FIG. 9;

[0027]FIG. 11 is a block diagram illustrating a latch array used tosample the clock signals, in the sampled clock unit of FIG. 10;

[0028]FIG. 12 is block diagram of a switchport (multiplexor) used by thesampled clock unit of FIG. 10;

[0029]FIG. 13 is a block diagram illustrating the retime latch of FIG.9;

[0030]FIG. 14 is a block diagram of another multiphase phase-lock loopusing self-correcting phase detector, in accordance with anotherembodiment of the present invention;

[0031]FIG. 15 is a block diagram illustrating the multiphase phasedetector used in the phase-lock loop of FIG. 14;

[0032]FIG. 16 is a block diagram of a self-correcting unit used by themultiphase phase detector of FIG. 15;

[0033]FIG. 17 is a block diagram of a sampled data unit used in theself-correcting unit of FIG. 16;

[0034]FIG. 18 is a block diagram of an XOR gate array used in theself-correcting unit of FIG. 16;

[0035]FIG. 19 is a block diagram of the multiplexor used by themultiphase phase detector of FIG. 15;

[0036]FIG. 20 is a timing diagram illustrating the various signalsassociated with a “retime state 1” wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0037]FIG. 21 is a timing diagram illustrating the various signalsassociated with a “retime state 2” wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0038]FIG. 22 is a timing diagram illustrating the various signalsassociated with a “retime state 3” wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0039]FIG. 23 is a timing diagram illustrating the various signalsassociated with a “retime state 4” wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0040]FIG. 24 is a timing diagram illustrating the various signalsassociated with a “retime state 5” wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0041]FIG. 25 is a timing diagram illustrating the multiphase clocksignals and error correction signals wherein the clock and data arealigned, for the self-correcting implementation of the presentinvention;

[0042]FIG. 26 is a timing diagram illustrating the multiphase clocksignals and error correction signals wherein the clock and lags the data(for retime state 1), for the self-correcting implementation of thepresent invention; and

[0043]FIG. 27 is a timing diagram illustrating a multiphase clocksignals and error correction signals where the clock leads the data (forretime state 2), for the self-correcting implementation of the presentinvention.

DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

[0044] The present invention provides an improved method and system forextracting a clock signal from a serial data stream. In one embodiment,the invention uses a multiplephase subharmonic clock from anon-return-to-zero (NRZ) stream to retime and deserialize the data. Inparticular, the implementations described below use a 5-phase onegigahertz (GHZ) voltage-controlled oscillator (VCO), and either a5-phase D-type phase detector or a 5-phase self-correcting phasedetector configured in a phase-lock loop (PLL), to recover the clock andretime a 5 gigabit per second NRZ data stream. Those skilled in the artwill appreciate, however, that the specific implementations disclosedherein are not to be construed in a limiting sense. For example, theinvention could be used for clock reduction factors other than 5, e.g.,7, 9, 11, etc., for single-rail rings oscillators, or 4, 6, 8, etc., fordifferential ring oscillators, or 4 for quadrature oscillators.

[0045] With reference now to the figures, and in particular withreference to FIG. 2, there is depicted a timing diagram for the 5 Gb/sNRZ data stream implementation of the invention. Five clock phases areavailable from a multiphase VCO operating at one GHz. An appropriatemultiphase VCO is disclosed in copending U.S. patent application Ser.No. __/______ filed on Nov. 30, 2000, and entitled “A HIGH-FREQUENCYLOW-VOLTAGE MULTIPHASE VOLTAGE-CONTROLLED OSCILLATOR,” which is herebyincorporated. The clock phases are separated equally and duty cycle is50% for each phase. Input data has timing jitter on all edges which hasa distribution around the mean time values T₁, T₂, . . . , T_(n).

[0046] Five synchronization states (SS₁-SS₅) are shown in FIG. 2,defining which of the rising edges of the five clock phases is mostclosely aligned with the edges (positive or negative) of data signal Dat any given point in time. SS₁ is asserted at time T₁ since the firstphase signal Ø₁ (at A) is in alignment, and is deasserted at time T₂since second phase signal Ø₂ (at B) becomes aligned and SS₂ is asserted.SS₂ stays asserted during the period from time T₂ to time T₃, when notransitions in the data are present, and deasserts when SS₄ is asserteddue to the fact that the fourth phase signal Ø₄ (at D) is aligned withtime T₃. Some synchronization states might not be asserted for briefperiods of time due to data transitions and the currently establishedtiming relationships (e.g., SS₅ in FIG. 2). Data is retimed (sampled inthe middle of the “eye” for optimum bit error rate (BER)) by choosingthe clock phase appropriate for the current synchronization state(“SynchState”). Data is sampled at time T₇ by Ø₄ (at L) since thecurrent SynchState is 1, i.e., the condition of SynchState=1 definesRetimeState=4 (RS₄). Similarly, SS₂, SS₃, SS₄, and SS₅ define the retimestates RS₅, RS₁, RS₂, and RS₃, respectively.

[0047]FIG. 3 shows a table which is used to determine the currentSynchState and RetimeState from serial data sampling the clocks.Transitions in the data (both positive and negative) are used to sampleall five phases of the clock and are held as binary values Q₁-Q₅ forØ₁-Ø₅, respectively. The “X” values in the table of FIG. 3 are examinedto generate the error signal for the PLL, according to the second tableshown in FIG. 4 (for the D-type detector implementation of the presentinvention). For example, if SynchState=1, then a zero value for Q₁indicates that the clock is late (“Clock Late wrt Data” value of 1),while a one value for Q₁ indicates that the clock is early (“Clock Latewrt Data” value of 0). The timing of the error signals is shown in FIG.2, where the clocks are determined to be either early or late withrespect to the data (for the D-type detector implementation of thepresent invention). Data sampling the clocks is illustrated in FIG. 2 attime T₆, where the sampled values of Ø₁-Ø₅ are latched to create valuesQ₁-Q₅ as shown in the timing diagram. The values of Q₁-Q₅ at T₆correspond to SynchState=4 and RetimeState=2, shown in FIG. 2 becomingasserted at T₆, while the previous SynchState and RetimeState becomedeasserted (SS₃/RS₁).

[0048] The clocks sample the data signal to retime the data.

[0049]FIG. 2 illustrates how the negative transition of the appropriateclock phase is used to sample the data in the center of the bitinterval. For example, during the period from T₄ to T₅, SynchState=2 andRetimeState=5 are asserted; therefore the negative edge of Ø₅ samplesthe data at T₁₀, resulting in the retimed data signal (Retimed D)changing to a low state. In general, for RetimeState=n (n=1 . . . 5), anegative transition of Ø_(n) samples D, and a positive transition of[1+mod₅(Ø_(n+2))] samples SD_(n) (the sampled data from Ø_(n)): anegative transition of Ø₁ samples D, positive transition of Ø₄ samplesSD₁; a negative transition of Ø₂ samples D, positive transition of Ø₅samples SD₂; a negative transition of Ø₃ samples D, positive transitionof Ø₁ samples SD₃; a negative transition of Ø₄ samples D, positivetransition of Ø₂ samples SD4; and a negative transition of Ø₅ samples D,positive transition of Ø₃ samples SD₅.

[0050]FIG. 5 shows a timing example for the condition wherein the clocksare generally aligned with the data, for the D-type detectorimplementation of the present invention. An error signal is generatedwhich becomes asserted at time T₁ due to Ø₁ being late with respect tothe rising edge of the data D for SS₁ asserted. The error remains highat time T₂ since Ø₂ is late with respect to the negative edge of D forSS₂ asserted. At time T₃ SynchState=4, Ø₄ leads D, and the error signaldeasserts. At time T₄ (SS₂) Ø₂ leads D and the error stays low, at timeT₅ (SS₃) Ø₃ lags D and error asserts, and at time T₆ (SS₄) Ø₄ leads Dand error deasserts. Since the phase detector has the characteristics ofa D-type flip-flop, it responds ideally to infinitesimal phasedifferences between the clock and the data. When the PLL is insteady-state, the average value of the error signal is 50% of the logicswing for random input data. The error signal is integrated by a chargepump or filter circuit to produce the control voltage (V_(c)) for theVCO (discussed further below). The control voltage causes the VCOfrequency to increase (V_(c) increasing) or decrease (V_(c) decreasing)to correct for the error.

[0051]FIG. 6 shows the timing for the clock lagging the data. Theaverage value of the error signal rapidly increases for this condition,causing the VCO frequency to increase rapidly. Similarly, FIG. 7 shows acorresponding rapid decrease in the average value of the error signalfor the clock leading the data, forcing the frequency of the VCO rapidlylower. Very rapid PLL acquisition is a consequence of this phenomena,but increased jitter caused by overcorrection during missing transitionsmay also occur.

[0052]FIG. 8 is a block diagram depicting a multiphase PLL 10 whichimplements the foregoing embodiment of the invention. An NRZ data streamis presented at the input to PLL 10. A 5-phase VCO 12 operating at oneGHz is connected to a D-type multiphase phase detector 14 which includesa retiming function. D-type multiphase phase detector 14 thus receiveseach of the signals Ø₁-Ø₅, as well as the data signal, and outputs alate clock error signal to a conventional charge-pump 16. Charge-pump 16creates a control (feedback) voltage for VCO 12 from the error signal.

[0053]FIG. 9 is another block diagram depicting the high-levelorganization of D-type multiphase phase detector 14. D-type multiphasephase detector 14 is comprised of a sampled clock unit 18, a retimelatch 20, synchronization logic 22, and retiming logic 24. Sampled clockunit 18 receives the data and five clock signals, and uses both edges ofthe data to sample the clocks. Retime latch 20 receives these inputs aswell, and uses the clocks to sample the data to create retimed data.Synchronization logic 22 generates the SynchStates according to thetable of FIG. 3, and provides the late clock signal. Retiming logic 24generates the RetimeStates according to the table of FIG. 4, andprovides those states to retime latch 20.

[0054]FIG. 10 illustrates exemplary components of sampled clock unit 18.Two sets of latch arrays 26 sample the clocks from the data signal toprovide the latched values (a suitable latch configuration is shown inFIG. 11). A switchport 28 (essentially a multiplexor, see FIG. 12)selects from among the inputs provided by the flip-flop arrays to outputthe appropriate data samples P₁-P₅, which are then provided tosynchronization logic 22 and retiming logic 24 (the “Q” values in FIGS.3 and 4).

[0055]FIG. 13 illustrates exemplary details of how retime latch 20selects the appropriate phase for capturing the data. The phase isselected by combining respective pairs of retime state signals andinverted phase signals using AND gates 30, and further combining theoutputs of AND gates 30 using a 5-input OR gate 32. A D-type flip-flop34 latches the output of OR gate 32 using the original data signal, toproduce the retimed data signal.

[0056] Simulations of the foregoing design for PLL 10 demonstrate thatphase acquisition time is more than an order of magnitude faster thanthat for alternate PLL designs. Operating the PLL at lower speeds savespower, allowing higher densities, and makes less-advanced technologiesviable alternatives. The use of a D-type phase detector offers not onlysignificantly reduced acquisition times, but also lower complexity, andless power dissipation. D-type phase detectors may require aidedfrequency acquisition or reduced VCO range to avoid lock at undesiredharmonics of the serial data, and may have higher steady-state jitterfor low data transition density. Other devices may be used to providethe on/off functionality of the early/late detection, such as asaturating amplifier.

[0057] In the foregoing design, the retiming state is used to select asignal that is indicative of whether the appropriate multiphase clock isearly or late with respect to the data signal. In an alternativeembodiment, the retiming state is used to sample the data to determinethe coarse phase error, and to detect the transition density for furtherrefinement of the phase error determination. This alternative design ofa PLL 40 constructed in accordance with the present invention isillustrated in FIG. 14. PLL 40 again uses a 5-phase VCO 12 operating atone GHz, but VCO 12 is now connected to a 5-phase self-correcting phasedetector 42 which includes a retiming function, as explained furtherbelow. A conventional charge-pump 16 is again used to create a controlvoltage for VCO 12, from the error signals UP and DN.

[0058]FIG. 15 depicts the high-level organization of self-correctingphase detector 42. Self-correcting phase detector 42 includes aself-correcting unit 44 which uses the clocks to sample data, amultiphase phase-detector 14 which uses data to sample the clock phasesand generate SynchStates and RetimeStates, and a multiplexor 48. Thedetails of multiphase phase detector 14 may be understood with referenceto FIGS. 9-13. Self-correcting unit 44 provides 5 sets of UP/DN signals,one of which is selected by multiplexor 48 to pass on to charge pump 16,as explained further below.

[0059] Self-correcting unit 44 is detailed in FIG. 16, and includes asampled data unit 50, and an XOR gate array 52. Sampled data unit 50receives the data signal and the clock signals as inputs, and has 10outputs which are further illustrated in FIG. 17. Sampled data unit 50provides the clock sampling of the data function which provides thesignals SD_(n) and SD_(n1) as described earlier (e.g., negativetransition of Ø₂ samples D, positive transition of Ø₅ samples SD₂). Thedata is sampled by providing the inverted multiphase clock signals to afirst set of five flip-flops 54, respectively, and providingnon-inverted clock signals to a second set of five flip-flops 56,respectively. Each of the flip-flops also receives either a data signalD or a sampeld data signal SD_(n).

[0060] The outputs of sampled data unit 50 are fed as inputs to XOR gatearray 52, which is further depicted in FIG. 18. XOR gate array 52 usesthese inputs to provide a set of 10 signals referred to herein as X_(n)and X_(n1), which are further explained below. The first five SD_(n)values (from flip-flops 54) are respectively combined with the datasignal using five XOR gates 58, to result in signals X_(n). These firstfive SD_(n) values are also respectively combined with the second set offive SD_(n1) values (from flip-flops 56) using five more XOR gates 60,to result in signals X_(n1). The X_(n) and X_(n1) signals are providedto multiplexor 48, which selects UP_(n) and DN_(n) in accordance withthe current RetimeState RS_(n). Multiplexor 48 is shown in FIG. 19. Eachof the retime state signals is fed to two different AND gates 62 and 64.Each AND gate 62 and 64 also receives a single one of the X_(n) andX_(n1) signals. The outputs of AND gates 62 are combined by a 5-input ORgate 66, and the outputs of AND gates 64 are combined by another 5-inputOR gate 68, to create the UP and DN signals for use by charge-pump 16.

[0061]FIG. 20 shows an example of the timing for RetimeState=1 for PLL40 for the steady state (i.e., clock and data aligned) conditions. Thedata D is sampled by the negative transitions of Ø₁ and is held as SD₁.SD₁ is sampled by the next positive transition of Ø₄ and is held asSD₁₁. An XOR gate compares D with SD₁ to create X₁ and another XOR gatecompares SD₁ and SD₁₁ to create X₁₁. During the time when RS₁ isasserted, a change in the state of D from the state of SD₁ causes X₁ tobecome asserted until the next negative transition of Ø₁ causes SD₁ andD to be equal again. If the negative transition of Ø₁ occurs in thecenter of the baud interval, then X₁ will have an average value of 50%.If the data leads the clock the average value will increase; similarly,the average value will decrease for the data lagging the clock. Alsoduring the time when RS₁ is asserted (i.e., RetimeState=1), a change inthe state of D from the state of SD₁ causes SD₁₁ to change state on thesubsequent positive transition of Ø₄, asserting X₁₁ for exactly one-halfof the baud interval/clock phase. In this manner a reference pulse fromX₁₁ is provided, against which the error pulse from X₁ can be compared.Finally, RS₁ is AND-ed with X₁ and X₁₁ to create the UP₁ and DN₁signals, respectively. For the steady state case, the areas under UP₁and DN₁ are equal; a capacitor charged/discharged from UP₁/DN₁ through acharge pump will not register a voltage change over the duration ofRetimeState1.

[0062]FIGS. 21, 22, 23, and 24 similarly show steady state timingrelationships for RetimeStates=2, =3, =4, and =5, respectively. It willbe noted that in those figures, the area under UP_(n) and DN_(n) areequal for the steady state case. FIG. 25 shows the timing involved withthe various UP_(n) and DN_(n) signals, and the control voltage after thecharge pump. The overall change in control voltage is zero for thesteady state case when data and clock are aligned. FIG. 26 shows anexample of the timing for RetimeState=1 for the clock lagging the data.Since Ø₁ should normally have its negative transition in the center ofthe eye when RS₁ is asserted, the average value of X₁ increases and UP₁is affected similarly (see FIG. 20). The average values of X₁₁ and DN₁remain at 50%. A positive change in control voltage will result fromsuch a phase relationship as shown by “V_(c) effective” in FIG. 26. FIG.27 shows an example of the timing for RetimeState=2 for the clockleading the data. Note the corresponding decrease in average value forX₂ and UP₂ when RS₂ is asserted compared to FIG. 21. Again, the averagevalue of X₂₁ and DN₂ remain at 50%. A negative change in control voltagewill result from such a phase relationship as shown by “V_(c) effective”in FIG. 27.

[0063] Although the invention has been described with reference tospecific embodiments, this description is not meant to be construed in alimiting sense. Various modifications of the disclosed embodiments, aswell as alternative embodiments of the invention, will become apparentto persons skilled in the art upon reference to the description of theinvention. It is therefore contemplated that such modifications can bemade without departing from the spirit or scope of the present inventionas defined in the appended claims.

1. A method of effectively extracting a clock signal from a data stream, comprising the steps of: generating a plurality of multiphase clock signals; creating a plurality of error signals, at least one error signal for each of the multiphase clock signals, using the data stream; selecting at least one of the error signals based on a plurality of retime state signals; correcting the multiphase clock signals using the at least one error signal to produce corrected multiphase clock signals; and sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal.
 2. The method of claim 1 wherein said generating step generates multiphase clock signals which are subharmonics of the data stream.
 3. The method of claim 1 wherein: said creating step creates, for each of the multiphase clock signals, an UP error signal and a DN error signal; said selecting step selects one of the UP error signals and one of the DN error signals; and said correcting step includes the step of applying the selected UP error signal and the selected DN error signal to inputs of a charge pump.
 4. The method of claim 3 wherein said generating step generates the multiphase clock signals using a multiphase voltage-controlled oscillator.
 5. The method of claim 4 wherein said correcting step further includes the steps of: generating a control voltage output of the charge pump using the selected UP and DN error signals; and applying the control voltage output of the charge pump to an input of the multiphase voltage-controlled oscillator.
 6. The method of claim 1 further comprising the step of selecting the corrected multiphase signal for said sampling step based on a plurality of synchronization states identifying which of the multiphase clock signals is most closely aligned with the data stream.
 7. The method of claim 6 wherein: each of the multiphase clock signals has at least one rising edge; and said step of selecting the corrected multiphase signal includes the step of using the synchronization states to define which of the rising edges of the multiphase clock signals is most closely aligned with an edge of the data stream.
 8. The method of claim 7 further comprising the step of defining the retime state signals using the synchronization states.
 9. The method of claim 8 wherein said sampling step further comprises the steps of: inverting the multiphase clock signals to produce inverted phase signals; combining respective pairs of the retime state signals and the inverted phase signals using a plurality of respective AND gates; combining the outputs of the AND gates using an OR gate; and latching the output of the OR gate using the data stream to produce the retimed data signal.
 10. A circuit for effectively extracting a clock signal from a data stream, comprising: means for generating a plurality of multiphase clock signals; means for creating a plurality of error signals, at least one error signal for each of the multiphase clock signals, using the data stream; means for selecting at least one of the error signals based on a plurality of retime state signals; means for correcting the multiphase clock signals using the at least one error signal to produce corrected multiphase clock signals; and means for sampling the data stream using one of the corrected multiphase signals to produce a retimed data signal.
 11. The circuit of claim 10 wherein said generating means generates multiphase clock signals which are subharmonics of the data stream.
 12. The circuit of claim 10 wherein: said creating means creates, for each of the multiphase clock signals, an UP error signal and a DN error signal; said selecting means selects one of the UP error signals and one of the DN error signals; and said correcting means applies the selected UP error signal and the selected DN error signal to inputs of a charge pump.
 13. The circuit of claim 12 wherein said generating means includes a multiphase voltage-controlled oscillator.
 14. The circuit of claim 13 wherein said correcting means further generates a control voltage output of said charge pump using the selected UP and DN error signals, and applies the control voltage output of said charge pump to an input of said multiphase voltage-controlled oscillator.
 15. The circuit of claim 10 further comprising means for selecting the corrected multiphase signal for said sampling means based on a plurality of synchronization states identifying which of the multiphase clock signals is most closely aligned with the data stream.
 16. The circuit of claim 15 wherein: each of the multiphase clock signals has at least one rising edge; and said means for selecting the corrected multiphase signal uses the synchronization states to define which of the rising edges of the multiphase clock signals is most closely aligned with an edge of the data stream.
 17. The circuit of claim 16 wherein the synchronization states define the retime state signals.
 18. The circuit of claim 17 wherein said sampling means: inverts the multiphase clock signals to produce inverted phase signals; combines respective pairs of the retime state signals and the inverted phase signals using a plurality of respective AND gates; further combines outputs of said AND gates using an OR gate; and latches an output of said OR gate using the data stream to produce the retimed data signal. 